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1.5A LOW VOLTAGE LOW DROPOUT CMOS REGULATOR
FSP2161
FEATURES
Low-Dropout Regulator Supports Input Voltages Down to 1.4V Output Voltage Available in 0.9V, 1.0V, 1.2V, 1.5V, 1.8V, 2.5V,2.8V,2.85V,3.0V, 3.3V Stable with a Ceramic Output Capacitor of 1.0uF or Higher Low Dropout Voltage:150mV at 1.5A Low Quiescent Current Over Temperature Shutdown Short Circuit Protection Low Temperature Coefficient Standard TO252 and TO263 Packages
GENERAL DESCRIPTION
The FSP2161 is a 1.5A CMOS LDO regulator that features a low quiescent current, ultra low input, output and dropout voltages, as well as over temperature shutdown. It is available in TO252 and TO263 packages. The fixed output voltage of the FSP2161 is set at the factory and trimmed to 2%. The FSP2161 is stable with a ceramic output capacitor of 1.0uF or higher. This family of regulators can provide either a stand-alone power supply solution or act as a post regulator for switch mode power supplies. They are particularly well suited for applications requiring low input and output voltage
APPLICATIONS
DSP, FPGA, and Microprocessor Power Supplies 1.2V Core Voltage for DSPs SATA Power Supply LCD TV/ Monitors Wireless Devices Communication Devices Portable Electronics Post Regulator for SMPS
PIN CONFIGURATION
1) TO252 (Top View) 2) TO263 (Top View)
PIN DESCRIPTION
Pin Number TO252 1 2 3 TO263 1 3 5 2 4 Pin Name VIN GND VOUT EN PWRGD Pin Function Input Ground Output Enable pin Power good
BLOCK DIAGRAM
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FSP2161
TYPICAL APPLICATIONS CIRCUITS
ABSOLUTE MAXIMUM RATINGS
Parameter Input Supply Voltage Maximum Output Current Output Pin Voltage Internal Power Dissipation Junction to Case Thermal Resistance (JC) Junction to Ambient Thermal Resistance (JA) Operating temperature Operating Junction Temperature Storage Temperature Maximum Junction Temperature Rating +4 PD/(VIN-VO) -0.3 to VIN+0.3 1200 7 90 -40 to 85 -40 to 125 -65 to 150 150 Unit V V mW / W / W C C C C
Lead Temperature (Soldering, 5 sec) 300 C Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability. All voltages are with respect to ground.
RECOMMENDED OPERATING CONDITIONS
Parameter Input Supply Voltage Operating temperature Operating Junction Temperature Rating 1.4 to 3.6 -40 to 85 -40 to 125 Unit V C C
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(VOUT = VIN + 0.5V, CIN = 1F, CO = 2.2F, TA= 25C unless otherwise specified.) PARAMETER Input Voltage Output Voltage Accuracy Short Circuit Current Ground Current Quiescent Current Line Regulation Load Regulation Error Temperature Coefficient Over Temperature Shutdown Over Temperature Hystersis Power Supply Ripple Rejection SYMBOL VIN VO ISC IGND IQ LNR LDR TC OTS OTH PSRR TEST CONDITIONS IO= 100mA VO < 0.3V IO= 1mA to 1.5A IO= 0mA IO= 10mA, VO 2.5V VIN =VO + 0.5V to VO + 1.5V IO= 10mA, VO2.5V VIN = 3.3V to 3.6V IO = 1mA to 1.5A MIN Note1 -2 1.0 90 0.5 0.5 0.5 40 150 50 55 55 35 330 220 50 40 330 220 150 120 40 600 150 1 %/V 1 2 %/A ppm/C C C dB 500 400 200 150 500 400 350 300 VRMS mV TYP MAX 3.6 +2 UNIT V % A A A
ELECTRICAL CHARACTERISTICS
FSP2161
IO = 100mA Vo =1.5V
IO = 500mA Dropout Voltage VDROP IO = 1.5A
f=100Hz f= 1KHz f= 10KHz VO= 0.9V VO= 1.0V 1.2V VO < 2.5V VO 2.5V VO= 0.9V VO= 1.0V 1.2V VO < 2.5V VO 2.5V
Output Noise
Vn
f = 10Hz to 100kHz
Note 1The minimum input voltage of the FSP2161 is determined by output voltage and dropout voltage. The minimum input voltage is defined as: VIN(MIN)=VO+VDROP
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APPLICATION INFORMATION
The FSP2161 family of low-dropout (LDO) regulators have several features that allow them to apply to a wide range of applications. The family operates with very low input voltage (1.4V) and low dropout voltage (typically 150mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode power supplies. The 1.5A output current make the FSP2161 family suitable for powering many microprocessors and FPGA supplies. The FSP2161 family also has low output noise (typically 40VRMS with 2.2F output capacitor), making it ideal for use in telecom equipment. External Capacitor Requirements A 2.2F or larger ceramic input bypass capacitor, connected between VIN and GND and located close to the FSP2161, is required for stability. A 1.0uF minimum value capacitor from VO to GND is also required. To improve transient response, noise rejection, and ripple rejection, an additional 10F or larger, low ESR capacitor is recommended at the output. A higher-value, low ESR output capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source, especially if the minimum input voltage of 1.4 V is used. Regulator Protection The FSP2161 features internal current limiting, thermal protection and short circuit protection. During normal operation, the FSP2161 limits output current to about 3A. When current limiting engages, the output voltage scales back linearly until the over current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C, thermal-protection circuitry will shut down. Once the device has cooled down to approximately 50C below the high temp trip point, regulator operation resumes. The short circuit current of the FSP2161 is about 1A when its output pin is shorted to ground. Thermal Information The amount of heat that an LDO linear regulator generates is: PD=(VIN-VO)IO. All integrated circuits have a maximum allowable junction temperature (TJ max) above which normal operation is not assured. A system designer must design the operating environment so that the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJ max). The two main environmental variables that a designer can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment for a linear regulator that is operating at a specific power level. In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as: Where: VI (avg) is the average input voltage. VO(avg) is the average output voltage. IO(avg) is the average output current. I(Q) is the quiescent current. For most LDO regulators, the quiescent current is insignificant compared to the average output current; therefore, the term VI(avg) xI(Q) can be neglected. The operating junction temperature is computed by adding the ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (RJC), the case to heatsink (RCS), and the heatsink to ambient (RSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation so that the object's thermal resistance will be lower.
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TYPICAL PERFORMANCE CHARACTERISTICS
FSP2161
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FSP2161
TYPICAL PERFORMANCE CHARACTERISTICSCONTINUED
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FSP2161
TYPICAL PERFORMANCE CHARACTERISTICSCONTINUED
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TYPICAL PERFORMANCE CHARACTERISTICSCONTINUED
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ORDERING INFORMATION
FSP2161XXXX Package Type: D: TO252 K: TO263 Output Voltage: 33: 3.3V 30: 3.0V 285: 2.85V 28: 2.8V 25: 2.5V 18: 1.8V 15: 1.5V 12: 1.2V 10: 1.0V 09: 0.9V Temperature Grade: Packing: A: Tape & Reel D: -40~85
MARKING INFORMATION
(1) TO252 (2) TO263
Logo
Logo
2161-VV
YYWWXX
Part Number: 2161-09: 0.9V 2161-10: 1.0V 2161-12: 1.2V 2161-15: 1.5V 2161-18: 1.8V 2161-25: 2.5V 2161-28: 2.8V 2161-285: 2.85V 2161-30: 3.0V 2161-33: 3.3V Internal Code Date Code: YY: Year (01=2001) WW: Nth week (01~52)
2161-VV
YYWWXX
Part Number: 2161-09: 0.9V 2161-10: 1.0V 2161-12: 1.2V 2161-15: 1.5V 2161-18: 1.8V 2161-25: 2.5V 2161-28: 2.8V 2161-285: 2.85V 2161-30: 3.0V 2161-33: 3.3V Internal Code Date Code: YY: Year (01=2001) WW: Nth week (01~52)
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FSP2161
PACKAGE INFORMATION
(1) TO252
Symbol A B C D E F S G H J K L M R
Min. 6.40 5.20 6.80 2.20 0.70 0.60 0.50 2.20 0.45 0 0.90 5.40 0.80
Dimensions In Millimeters Nom. 6.60 5.35 7.00 2.50 2.30REF 0.80 0.75 0.60 2.30 0.50 0.07 1.20 5.60 1.00
Max. 6.80 5.50 7.20 2.80 0.90 0.90 0.70 2.40 0.55 0.15 1.50 5.80 1.20
Dimensions In Inches Nom. 0.264 0.214 0.280 0.100 0.092REF 0.028 0.032 0.024 0.030 0.020 0.024 0.088 0.092 0.018 0.020 0 0.003 0.036 0.048 0.216 0.224 0.032 0.040 Min. 0.256 0.208 0.272 0.088
Max. 0.272 0.220 0.288 0.112 0.036 0.036 0.028 0.096 0.022 0.006 0.060 0.232 0.048
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FSP2161
2) TO263
10.90
E
L2
D L
9.10
15.70
2.50
1.00
e
1.70
B
Land Pattern Recommendation (Unit: mm)
A C2 C L1
Symbol A B C C2 D E e L L1 L2
Min. 4.07 0.51 0.36 1.14 8.20 9.65 1.57 14.45 1.78
Dimensions In Millimeters Nom. Max. 4.46 4.85 0.84 1.02 0.50 0.74 1.27 1.65 9.15 9.65 10.16 10.67 1.71 1.85 15.24 15.88 2.54 2.79 2.92
Min. 0.163 0.020 0.014 0.046 0.328 0.386 0.063 0.578 0.071
Dimensions In Inches Nom. 0.176 0.033 0.020 0.050 0.360 0.400 0.068 0.600 0.100
Max. 0.194 0.041 0.030 0.066 0.380 0.427 0.074 0.635 0.110 0.115
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